1. Field of the Invention
The present disclosure relates generally to memory devices and, more particularly, the present invention relates to phase change memory devices.
A claim of priority is made to Korean Patent Application No. 10-2006-003272, filed on Jan. 11, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
Phase change random access memory devices (PRAM) store data using a phase change material, such as, for example, a chalcogenide alloy, that transforms into a crystalline state or an amorphous state during cooling after heat treatment. Each state of the phase change material has different resistance characteristics. Specifically, the phase change material in the crystalline state has low resistance and the phase change material in the amorphous state has high resistance. The crystalline state is typically referred to as a “set state” having a logic level “0”, and the amorphous state is typically referred to as a “reset state” having a logic level “1”.
In the phase change memory devices, data is written using Joule heat. This Joule heat is generated when a write current is supplied to the phase change material having a predetermined resistance. Specifically, the phase change material is heated to at least a melting temperature of the material and then rapidly cooled, so that the phase change material transforms into the amorphous state. Alternatively, the phase change material is heated to temperature that is higher than a crystallization temperature but less than the melting temperature, kept at the temperature for a predetermined time, and then cooled. By this process, the phase change material transforms into the crystalline state.
Furthermore, in order to provide high capacity and high integration in the phase change memory devices, the phase change memory devices can be implemented by a hierarchical bit line structure using global bit lines and local bit lines. In this case, there may be a difference in length between phase change memory cells that are coupled to local bit lines distant from a wiring circuit and/or a reading circuit and phase change memory cells coupled to local bit lines close to the writing circuit and/or the reading circuit. This difference in length may affect the operation of the phase change memory device. That is, because resistance exists on the individual global bit lines, resistance from the writing circuit and/or the reading circuit to the selected phase change memory cell may not be uniform. Instead, the resistance may vary according to the position of the selected phase change memory cell with respect to the writing circuit and/or the reading circuit. Thus, a difference in resistance depends on a physical distance between the cell and the writing/reading circuit.
These differences in resistance between phase change memory cells and reading/writing circuits may lead to undesirable consequences. In particular, as described above, the phase change memory devices write data using the write current. This write current may be sensitive to the difference in resistance. Accordingly, a write current to be applied to the phase change memory cells that are coupled to the local bit lines distant from the writing circuit and/or the reading circuit may be smaller than a write current to be applied to the phase change memory cells that are coupled to the local bit lines close to the writing circuit and/or the reading circuit. This difference in write current may lead to errors in the programming operations of phase change memory devices.